1. Technical Field
The present invention relates generally to the field of computer memory and more particularly, to multiple synchronous dynamic random access memory (DRAM) systems requiring faster performance.
2. Background
In recent years, the free fall of processor cycle times to levels well below access times of most dynamic random access memories has generated extensive research and development, the result of which has been the development of several generations of synchronous memory devices. Virtually all previously available semiconductor dynamic random access memory (DRAM) and many static random access memory (SRAM) devices used asynchronous clocking systems in that the clocking signals necessary to perform memory access functions are not synchronized to the associated system processor. Although memories were accessed by signals sent by the processor, the exact time interval between the time a request was sent to a memory and the time a response was received was dependent on the particular internal features of the memory. Thus, it was necessary for system designers to allow for the “worst case” response time between requests for information and the anticipated time the information was available, which necessarily wasted time in the handling of many memory functions.
Improvements in semiconductor processing technology has enabled logic components such as microprocessors to operate at clock rates in excess of 3 GHz. Memory system clock rates have not kept pace because of the nature of DRAM memory devices. In order to perform well with these higher speed processors, synchronous dynamic random access memories (SDRAMs), operable with clock rates of up to 266 MHz and data rates of up to 533 M Bits per second, have been designed. SDRAMs are responsive to a high frequency clock signal generated by the system clocking circuitry often running at a clock multiple versus the processor, which renders all internal activity within the memory “synchronous” with other devices responsive to the same (or related) clock signal(s). In the synchronous approach, all SDRAM address and control inputs are sampled at the positive edge of the input clock, and all SDRAM outputs on recent DDR (Double Data Rate) SDRAMs are valid on subsequent positive and negative edges. This technique permits input/output transactions to take place on every clock cycle. SDRAMs can simplify both the overall system design and the memory-management subsystem, because the main memory operates in a deterministic, synchronous nature relative to the system clock.
As frequencies increase and cycle times decrease, memory designers are looking for additional ways to improve memory performance and timing margins. One element that can be improved is the timing latency component due to the simultaneous switching affect of all the drivers to the SDRAMs switching in the same direction at the same time. This delay contribution is known as simultaneous switch time (tSS). In recent low cost designs, this delay adder for tSS was as much as 1.06 ns. This contribution was 14% of the total timing budget for a memory subsystem running at a 7.5 ns cycle time.
Solutions to reduce the simultaneous switching delay adder include higher priced packaging, splitting the function across several components or running the memory at an increased cycle time.
Increased number of address/command signals due to larger DRAM or module densities only add to the simultaneous switching time delays for high performance/low cost memory solutions. The price tag for two single 14 bit 1:2 registers is usually less than about $2.00.
Furthermore, the concept of driving buses with half of the drivers providing non-inverting polarities and the other half of the drivers providing inverted polarities is a known way of reducing simultaneous switching affects. But this technique does not cover devices receiving those signals to accept the inverted signal polarity and still function as if they received the non-inverted signal polarity.
Further, synchronous memory devices do not include the ability to be programmed to accept non-inverted or inverted address/command signals, so this technique has not previously been viable.